Plural electrode composite constant current-gain transistor for logic circuit



Feb. 8, 1966 D. CORDERO 3,

PLURAL ELECTRODE COMPOSITE CONSTANT CURRENT-GAIN TRANSISTOR FOR LOGIC CIRCUIT Filed April 23, 1963 Sheets-Sheet l flee 14. @7018 2979a: 13., I 27 22 807 47 f; 37 4e M 2 74 7! 1 130 (6+!) 1* 11 (flwmfg fwszlro.

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Feb. 8, 1966 D. CORDERO PLURAL ELECTRODE COMPOSITE CONSTANT CURRENT-GAIN Filed April 25, 1963 TRANSISTOR FOR LOGIC CIRCUIT 3 Sheets-Sheet 2 I fi Pregnancy- D/OGEA/ES (7020520,

Iwe/wae Feb. 8, 1966 n. CORDERO 3,234,405

PLURAL ELECTRODE COMPOSITE CONSTANT CURRENT-GAIN TRANSISTOR FOR LOGIC CIRCUIT Filed April 23, 1963 3 Sheets-Sheet 5 Cine? Frey/en: 9

D/06EA/ES EaRoEQa,

Inna/m United States Patent of Delaware Filed Apr. 23, 1963, Ser. No. 27 4,986

11 Claims. (Cl. 307-885) This invention relates to transistors and more particularly to the provision of circuitry which is electrically equivalent to a transistor and which is characterized by a current-gain which is relatively insensitive to temperature changes and radiation levels.

It is well known that many electrical parameters of transistors are sensitive to radiation and temperature larly to the provision of circuitry which is electrically changes. Of special interest is the value of 5, which may be defined as the ratio of the collector current to the base current for either small signal A.C. or large signal D.C. conditions. It is often desirable to provide transistors capable of operation in a circuit over wide radiation and temperature changes in-whichthe of the transistor remains substantially constant.

Prior efforts to accomplish this end have concerned themselves with altering the physical parameters of the transistors, such as the thickness of the base region.

Another technique often employed to effect 5 stabilization with substantial changes in temperature has been to provide an electrical network to maintain a constant operating point on the transistor output characteristic, such as by use of a voltage divider network. One disadvantage of such a technique is the fact that a relatively large amount of power is consumed and the degree of stabilization is limited. Furthermore, this technique does not effectively serve to appreciably control the effective AG. 5 even though it does enhance the DC. 5 stabilization. These techniques have not been found to be wholly satisfactory as the results are not generally reproducible or consistent. These techniques have not resulted in sufficient 5 insensitivity to temperature variation often encountered in the environment in which the circuit may be required to operate.

In vie-w of the disadvantages of the prior art approaches, a different approach was sought which did not inherently possess the above-mentioned limitations. Thus, a transistor circuit having three external terminals comparable to the base, emitter and collector electrode terminals of an ordinary transistor was believed to offer the best solution, if such a design could be achieved. Such an approach was taken in copending patent application Serial No. 250,060, entitled, Transistor Technology, by James L. Buie, also assigned to the present assignee. In this copending patent application there is disclosed an inverse feedback circuit design employing two transistors of identical conductivity type interconnected in such a manner as to effectively render what may be viewed as one composite transistor relatively insensitive to substantial changes in temperature and radiation level during operation. The present invention is directed toward such a composite transistor using two transistors of opposite conductivity types, and without the use of an external feedback loop.

Accordingly, it is an object of the present invention to provide the equivalent of a present art transistor which is substantially insensitive to changes in temperature and radiation level.

It is also an object of the present invention to provide the equivalent of a present art transistor having a constant currenPgain.

It is another object of the present invention to provide a transistor circuit network which behaves electrically as a single prior art transistor in most respe ts, save that it is substantially insensitive to changes in temperature and radiation level.

It is a further object of the present invention to provide a transistor circuit network which behaves electricaily as a single transistor in most respects except that the effective 5 of the network is substantially insensitive to changes in temperature and radiation level.

It is yet another object of the present invention to provide a transistor circuit network of the character described which is compatible with either linear or nonlinear transistor circuits.

It is a still further object of the present invention to provide a circuit of the character described which may be readily fabricated in accordance with present art transistor technology.

It is a still further object of the present invent-ion to provide a transistor circuit network which behaves electrically as a single transistor in most respects and wherein the effective current-gain may be made dependent in a predetermined manner upon changes in radiation and temperature.

The novel features which are believed to be characteristic of the present invent-ion, both as to its organization and method of operation, together with further objects and advantages thereof will be better understood from the following description considered in connection with the accompanying drawings in which a presently preferred embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

In the drawings:

IGURE 1 is a schematic diagram of the basic present invention circuitry, FIGURE 1A showing the basic circuitry using a PNP input transistor and an NPN output transistor, FIGURE 13 showing the basic circuitry using an NP'N input transistor anda PNP output transistor;

FIGURE 2 is a circuit diagram showing the basic present invention circuitry coupled in a Darlington arrangement;

FIGURE 3 is a circuit diagram showing an alternative Darlington connection;

FIGURES 4-6 are circuit diagrams showing various coupling methods;

FIGURE 7 shows how the present invention circuitry can be applied as a low-pass filter, FIGURE 7A being a circuit diagram, and FIGURE 78 being a graph showing the circuit-current-gain plotted as a function of frequency;

FIGURE 8 shows how the present invention circuitry can be applied as a high-pass filter, FIGURE 8A being a circuit diagram, and FIGURE 8B being a graph showing the circuit current-gain plotted as a function of frequency;

FIGURE 9 shows how the present invention circuitry can be applied as a bandpass filter, FIGURE 9A being a circuit diagram, and FIGURE 93 being a graph showing the circuit current-gain plotted as a function oi frequency;

FIGURE 10 is a schematic and graphic representa tion showing how the basic circuitry of FIGURE 1A car provide various filter functions by proper selection 0 transistor 5, FIGURE 10(a) showing the 5 of the inpu transistor plotted as a function of frequency, FIGURI 10(b) showing the 5 of the output transistor plotted a a function of frequency, and FIGURE 10(0) showin the overall 5 plotted as a function of frequency;

FIGURE 12 is a schematic diagram showing the use.

of multiple-emitter transistors in the present invention circuitry to provide a NOR gate circuit.

Referring now to the drawings, there is shown in FIG- URE 1A the schematic diagram of a first embodiment of the basic present invention circuitry utilizing a PNP transistor 20 and an NPN transistor 30. The transistor 20 will be designated as the'input transistor and it includes a base electrode 21, an emitter electrode 22 and a collector electrode 23. The transistor 30 is designated as the output transistor and it includes a base electrode 31, an emitter electrode 32 and a collector electrode 33. The base electrodes 21 and 31 of the input and output transistors are interconnected by an electrical lead 25. The collector electrode 23 of the input transistor 20 is connected by an electrical lead 26 tothe emitter electrode 32 of the output transistor 30, the electrical lead 26Vbeing grounded, as shown. The emitter electrode 22 of the input transistor 20 is connected by an electrical lead 27 to an input terminal 35. The collector electrode 33 of the output transistor 30 is connected by an electrical lead 28 to an output terminal 36. A common terminal 37 is connected to the grounded electrical lead 26.

The entire circuit of FIGURE 1A may be viewed as a composite electrical translating elementhaving an input electrode, an output electrode and a common electrode, :onnections to these electrodes being made through the fespective input, output and common terminals 35-37. More specifically, the circuit of FIGURE 1A can be liewed as a composite NPN transistor having a base coniection to terminal 35, a collector connection to terminafi i6 and an emitter connection to terminal 37.

The circuit of FIGURE 1A will now be described as its operation with major emphasis being placed upon he current-gain of the composite device. It is to be .nderstood that the term ,8, as used herein, is applicable 3 both small signal AC. and large signal D.C. condions in the various'present invention embodiments. By iterconnecting the two transistors as shown, the currentain of the composite device will be substantially con- :ant with variations in temperature and radiation level. I the present state of the art, practicality dictates that re overall circuit be substantially greater than unity. ence, the current-gain of the output transistor 30, identi- :d by the reference notation [3 should be relatively rge with respect to the p of the input transistor 20, as entified by the reference notation p Yet B should larger than unity, the presently preferred range of ,8 :ing about 5-50. The presently preferred range of ,8 about 50-500. Of course, other values of [i and [i retionships could be chosen should it be desired to provide extremely low overall circuit [3.

A typical practical example of the circuit of FIG- RE 1A uses an input transistor 20 having a currentin characteristic of 20 (,6 =20), and an output trantor 30 having a current-gain characteristic of 200 =200). Therefore, [3 /[32 =10, which is also subntially equal to the current gain of the composite dee, 13 as will now be shown.

The input current flows through the input terminal 35 1 can be viewed as the base current, 1 of the com ;ite device. The overall current gain of the composite ice, 6 can be determined with reference to the ues of current indica ed on the dia of LE 1A.

The emitter current of the input transistor 20 is I the collector current of that transistor then being fiZO B l 2o+ The base current of the input transistor 20, which is also the base current of the output transistor 30, is then n 204- The emitter current of the output transistor 30 is (l 30'i B 520+ 1 The collector current of the output transistor 30, which is also the output current of the composite device, is

The current gain of the composite device then,

530 3 Ban +l Bakt' 5211+l B B2o+ ;It has been found that in this present invention circuitry ,8 =,B /-K, wherein K is a constant. And, when 13 is large with respect to B [3 being substantially greater than one, the current gain of the device is substantially equal to the ratio 3 3 and so equal to the constant, K. V

In FIGURE 1B of the drawing, there is shown the basic present invention circuitry utilizing an NPN input transistor and a PNP output transistor to provide a composite PNP transistor having a constant current-gain. The NPN input transistor is identified by the reference numeral 40, and includes a base electrode 41, an emitter electrode 42 and a collector electrode 4.3. The PNP output transistor is identified by the reference numeral 50, and includes a base electrode 51, an emitter electrode 52 and a collector electrode 53. The base electrodes 41 and 51 of the input and output transistors are interconnected by an electrical lead 45. The collector electrode 43 of the input transistor 40 is connected by an electrical lead 46 to the emitter electrode 52 of the output transistor 50, the electrical lead 46 being grounded, as shown. The emitter electrode '42 of the input transistor 40 is connected by an electrical lead 47 to an input terminal 55. The collector electrode 53 of the output transistor 50 is connected by an electrical lead 48 to an output terminal 56. t A common terminal 57 is connected to the grounded electrical lead 46. Thus, it is seen that the circuitry of FIGURE 1B is identical with that of FIGURE 1A with the exception of reversed transistor conductivity types, i.e., NPN substituted for PNP and vice versa.

The entire circuit of FIGURE 1B may be viewed as a composite PNP transistor having a base connection to terminal 55, a collector connection to terminal 56 and an emitter connection to terminal 57. The preceding discussion concerning the various transistor {5* characteristics and values of current indicated on the diagram of FIGURE 1A apply with equal force to the circuitry of FIGURE 1B, the current gain of the composite device of FIGURE 13 again being equal to the constant K.

In FIGURE 2 of the drawings, there is shown an. adaptation of the present invention basic circuit of FIG- URE 1A in a so-called Darlington circuit configuration. This embodiment utilizes four transistors 100, 110, 120 and 130. The transistor is of the PNP type and includes a base electrode 101, an emitter electrode 102 and a collector electrode 103. The transistor is of the NPN type and. includes a base electrode 111, an emitter electrode 112 and a collector electrode 113. The transistor is of the PNP type and includes a base electrode 121, an emitter electrode 122 and a collector electrode 123. The transistor is of the NPN type and Qcfl includes a base electrode 131, an emitter electrode 132 and a collector electrode 133.

The emitter electrode 162 of the transistor 1011 is connected to an input terminal 105 by an electrical lead 106. The base electrodes 101 and 111 of the transistors 160 and 110 are interconnected by an electrical lead 107. The collector elect-rode 103 of the transistor 100 is connected by an electrical lead 108 to the emitter electrode 112 of the transistor 119, the emitter electrode 112 also being connected to the emitter electrode 122 of the transistor 120 by an electrical lead 116.

The base electrodes 121 and 1 31 of the transistors 120 and 130 are interconnected by an electrical lead 117. The collector electrode 113 of the transistor 1 10 is connected to an output terminal 125 by an electrical lead 126. The collector electrode 133 of the transistor 130 is connected by an electrical lead 127 and the electrical lead 126 to the output terminal 125. The collector electrode 123 of thetransistor 120 and the emitter electrode 132 of the transisor-130 are connected to a common terminal 135 by an electrical lead 136, this common terminal being grounded, as shown.

In the circuit of FIGURE 2, transistors 100 and 110, comprising the input set of transistors, are connected in the basic manner of FIGURE 1A and, for ease of explanation only, are specified to have identical [3, this ,8 being indicated by the reference notation 6 Similarly, the transistors 120 and 160, comprising the output set, are specified to be of identical B, this being identified by the reference {3 Viewing the circuit of FIGURE 2 as a composite Darlington circuit configuration having an input terminal 165, and output terminal 125 and a common terminal 135, the input current flowing through the input terminal 165 will be designated I since, in a normal Darlington circuit, the input is applied to the base electrode of an input transistor. Under these specified notations for [3 and input current, the diagram of FIG- URE 2 is labeled to show the currents flowing in various parts of the circuit, these currents being expressed in terms of the input current I and the ,8 of the input and output transistor sets, {3 and [3 Referring to these notations, it can be shown that the output current I is:

owa

and

In FIGURE 3 of the drawing, there is shown another adaptation of the present invention basic circuitry to provide another embodiment of a Darlington circuit configuration. The circuit utilizes first and second PNP transistors 60 and '70, and third and fourth NPN transistors 80 and 90, the transistors having respective base electrodes 61, '71, 81 and 91, respective emitter electrodes 62, 72, 82 and 92, and respective collector electrodes 63, 73, 83 and 93. The emitter electrode 62 of the transistor 60 is connected to an input terminal 65 by an electrical lead 66. The collector electrodes 63 and 73 of the two PNP transistors are interconnected by an electrical lead 68, the lead 63 being grounded as shown. The base electrode 61 of the transistor 60 is connected by an electrical lead 69 to the emitter electrode 72 of the transistor 70. i

The base electrodes 71 and 81 of the transistors 70 and 80 are interconnected by an electrical lead 76. The emitter electrode 82 of the transistor 30 is connected to the base electrode 91 of the transistor 90 by an electrical lead 77. The collector electrodes 83 and 33 of the transistors 80 and 90 are connected by an electrical lead 84 to an output terminal 85. The emitter electrode 92 of the transistor 96 is coupled to a grounded common terminal 95.

The entire circuit of FIGURE 3 may be viewed as a composite Darlington circuit having respective input, output and common terminals 65, 85 and 95. The current gain of the NPN output transistors should be higher than the current gain of the PNP output transistors, the presently preferred [3 range for the NPN output transistors 86 and 90 being about 10-500 and the presently preferred ,6 range for the PNP input transistors 60 and 70 being about 550. Neither the PNP transistors nor the NPN transistors need be of an identical [3, the overall current gain, 5 being substantially constant with varying temperature and radiation level throughout the stated B ranges. For ease of explanation, in the illustrated embodiment of FIGURE 3, PNP transistors 60 and 70 having identical ,8 are selected, the B of each of these transistors being indicated by the reference symbol 5 Similarly, NPN transistors 80 and 99 having identical ;8 are selected, the B of these transistors being indicated by the reference symbol 5 By selecting PNP transistors having an identical ,8 and NPN transistors of identical 5, the overall current gain of the circuit (5 then becomes:

flan/so (500/70 1 2 (Bro/7o 1 2 1 50/70 1 Thus, it is seen that the overall circuit [3 is a function of the squares of the individual transistor 5 characteristics and, since the ratio of the individual transistor [3 characteristics remains constant with varying temperatures and radiation level, the circuit 8 is also constant.

In FIGURES 4, 5 and 6 of the drawings, there are shown various combinations of the basic circuitry of FIGURES 1A and 1B interconnected to form an integrated amplifier chain. Referring specifically to FIGURE 4, there is shown an integrated amplifier chain formed by cascadingtwo of the composite PNP transistors of FIGURE 1A. Four transistors are utilized in this embodiment, these transistors being identified by the reference numerals 141), 150, 160 and 170.

The transistor is of the PNP type and includes a base electrode 141, an emitter electrode 142 and a collector electrode 143. The transistor is of the NPN type and includes a base electrode 151, an emitter electrode 152 and a collector electrode 153. The transistor is of the PNP type and includes a base electrode 161, an emitter electrode 162 and a collector electrode 163. The transistor 170 is of the PNP type and includes a base electrode 171, an emitter electrode 172 and a collector electrode 173.

The base electrodes 141 and 151 of the transistors 140 and 150 are interconnected by an electrical lead 145. The collector electrode 143 of the transistor 140 is connected by an electrical lead 146 to the emitter electrode 152 of the transistor 150, the electrical lead 146 being grounded, as shown. The emitter electrode 142 of the transistor 140 is connected by an electrical lead 147 to an input terminal 155. The collector electrode 153 of the transistor 150 is connected by an electrical lead 148 to the emitter electrode 162 of the transistor 160. A source of operating voltage, designated Vcc, is applied between ground and a terminal 156, the terminal 156 being coupled by a resistor 157 to the electrical lead 148 interconnecting the transistors 150 and 160.

The collector electrode 173 of the transistor 170 is connected to an output terminal by an electrical lead 166. The base electrodes 161 and 171 of the transistors 160 and 171 are interconnected by an electrical lead 167. The collector electrode 163 of the transistor 160 is connected by an electrical lead 168 to the emitter electrode 172 of the transistor 170, the electrical lead 168 being grounded, as shown. A common terminal 175'isconnected to the grounded electrical lead 168.

The entire circuit of FIGURE 4 may be viewed asf two cascaded composite NPN transistors, the positive terminal of the operating voltage source V being con-- PNP transistor of FIGURE 1B with'the composite NPN transistor of FIGURE 1A. The four transistors utilized. in this embodiment are identified by the reference nu morals 180, 190, 209 and 210. The transistor 180 is of the PNP type and includes a base electrode 181, an emitter electrode 182 and a collector electrode 183. Thetransistor 190 is of the NPN type and includes a base: electrode 191, .an emitter electrode 192 and a collector lead 226 to the emitter electrode 232 of the transistor electrode 193. The transistor 200 is of the NPN typeand includes a base electrode 201, an emitter electrode 292 and a collector electrode 203. The transistor 210 is of the PNF type and includes a base electrode 211,. 1

an emitter electrode 212 and a collector electrode 213.

The transistors 180 and 190 form the composite NPN The transistors 200 and 210 form the composite PNP' transistor'ofFIGURE 1B, the base electrodes 201and 211 of the transistors 200 and 210 being interconnected by an electrical lead 197. The collector electrode 213 of the transistor 210 is coupled to an output terminal 265 by an electrical lead 206, the collector electrode 213" also being coupled to ground through a load resistor 2%)7. The collector electrode 203 of the transistor 200' is coupled to the emitter electrode v212 of the transistor 21tl'by an electrical lead 208. A common terminal 215 is coupled to ground, as shown. A voltage input terminal zldis coupled to the electrical'lead 208, a source of operating voltage, V being connected between ground'and the terminal 216. The source of operating voltage V is polarized, as shown, with its negative terminal grounded.

The circuit of FIGURE 6 is the opposite of the circuit of FIGURE 5 in that it shows an integrated amplifier chain formed by cascading the composite NPN transistor of FIGURE 1A with the composite PNP transistor of FIGURE 1B, the composite PNP transistor including transistors 229 and 230, the composite NPN transistor including transistors 240 and 250. The transistor 220 is of the NPN type and includes a base electrode 221, an emitter electrode 222 and a collector electrode 223. The transistor 230 is of the NPN type and includes a base electrode 231, an emitter'electrode 232 and a collector electrode233. The transistor 240 is of the PNP type and includes a base electrode 24-1, an emitter electrode 242 and a collector electrode 243. The transistor 250 is of the NPN type and includes a base electrode 251, an emitter electrode 252 and a collector electrode 253.

The transistors 220 and 230 form the composite PNP transistor of FIGURE 1B, the base electrodes 221 and 231 of the transistors 220 and 230 being interconnected by an electrical lead 225. The collector electrode 223 ofthe transistor 220 is interconnected by an electrical 230, the electrical lead 226 being grounded, as shown. The emitter electrode 222 of the transistor 220 is connected by an electrical lead 227 to aninput terminal 235. The collector electrode 233 of the transistor 230 is coupled by an electrical lead 236 to the emitter electrode 242 of the transistor 240.

The transistors 24-0 and 250 form the composite NPN transistor of FIGURE 1A, the base electrodes 2.41 and .251 of the transistors 240 and 250 being interconnected by an electrical lead 237. The collector electrode 243 of the transistor 240 is coupled by an electrical lead 238 to the emitter electrode 252 of the transistor 250. The collector electrode 253 of the transistor 250 is coupled to an output terminal245 by an electrical lead 246, the collector electrode 253 being coupled to ground through a load resistor 247. A common terminal 255 is connected to ground.

A voltage input terminal 256 is conected to the electrical lead 238 and a source ofoperating voltage V is coupled between the terminal 256 and ground. The operating voltage source V is polarized, as shown, with its positive terminal grounded. The integrated amplifier chains of FIGURES 5 and-6 also provide the desired advantages of an overall circuit 6 which is relatively insensitive to changes in temperature and radiation level.

FIGURES 7, 8 and 9 of the drawings illustratehow the frequency characteristic of the current gain of the basic circuit of FIGURE 1A can be altered through the use of capacitors, to thereby provide various types of frequency responses. Referring specifically to FIGURES 7A and 73, there is shown the basic circuit of FIGURE 1A to which a single capacitor has been added to provide a low-pass filter characteristic. Forease of explanation, like reference characters refer to identical components throughout the FIGURES 1A, 7A, 8A, 9A, 10 and 11. The desired low-pass filter characteristic is obtained in the circuitry of FIGURE 7A by the connection of a capacitor 261 between the electrical lead .25 and ground. Sincethe reactance of the capacitor 261 decreases with increasing frequency, it acts as a lowpass filter intercoupling the input and output transistors 2t) and 30. FIGURE 73 of the drawings is a graph showing the current gain of the composite circuit, 5 logarithmically plotted as a function of frequency.

FIGURE 8A of the drawings shows how a capacitor can be added to the basic circuitry of FIGURE 1A to provide a high-pass filter characteristic. In this embodiment, a capacitor 262 is coupled between the emitter electrode 22 of the transistor 20 and the electrical lead 25 interconnecting the input and output transistors. Since the capacitive reactance of the capacitor 262 decreases with increasing frequency, at very low frequencies the capacitor acts as a shunt of extremely high impedance (approaching an open circuit) across the emitter and base of the transistor 20. At extremely high frequencies, on the other hand, the low impedance of the capacitor 262 approaches a short circuit across the emitter and base electrodes of the'transistor 28 to directly couple input'signals to the 'base electrode 31 of the output transistor 30. In FIGURE 8B of the drawings, the overall circuit 3 of the composite device of FIGURE 8A is shown logarithmically plotted as a function of frequency.

In FIGURE 9A of the drawings, there is shown the basic circuitry of FIGURE 1A to which has been added both of the capacitors 261 and 262 to thereby provide a composite circuit exhibiting a bandpass characteristic, the circuit of FIGURE 9A resulting from a combination of the circuits of FIGURES 7A and 8A. In FIGURE 9B of the drawings, the overall circuit ,8 of the composite transistor of FIGURE 9A is shown logarithmically plotted as a function of frequency. At extremely low frequencies, the very high impedances of the capacitors 261 and 262 result in little effect on the circuit, thereby maintaining a constant current gain. At extremely high frequencies, on the other hand, the short-circuiting effect provided by the very low irnpedances of the capacitors 261 and 262 results in insignificant output current from the circuit. In the intermediate frequency range, the impedances of the capacitors 261 and 262 provide varying effects upon the current-gain characteristics. Typically, the capacitance of the capacitor 261 is significantly smaller than the capacitance of the capacitor 2&2, in accordance with the particular bandpass characteristic desired. As the frequency of the input signals increases above a particular frequency, designated by the reference symbol f in FIGURE 9B, the decreasing impedance of the capacitor 262 results in an increase in circuit gain in the manner shown in FIGURE 8B, the capacitor 262 acting primarily as a coupling capacitor at higher frequencies. As the frequency is increased above the frequency designated by the reference symbol f in FIGURE 9B, the decreasing impedance of the capacitor 261 provides a shunting effect across the input of the transistor 39. As the frequency of the input increases still higher, the low impedance of the capacitor 261 effectively short circuits the input of the transistor 30, thereby resulting in an insignificant circuit output. Therefore the overall current-gain characteristic of the composite device is of the desired bandpass configuration. Although the circuits of FIG- URES 7-9 illustrate various frequency characteristics attainab-le upon the addition of capacitors to the composite NPN transistor of FIGURE 1A, the foregoing concepts are equally applicable to the composite PNP transistor of the basic circuitry of FIGURE 1B.

Turning now to FIGURES 10 and 11 of the drawings, there are shown embodiments in which various frequency characteristics can be obtained for the composite NPN transistor of FIGURE 1A, without the use of capacitors or other external circuitry. The desired characteristics are attained by selection of the individual PNP and NPN transistors forming the composite device, the selection being made on the basis of the 6 of each of the individual transistors. For example, in the circuit of FIGURE 10, a PNP input transistor 20 having the B characteristic shown in FIGURE 10(a) is chosen. An NPN output transistor 30 having the characteristics shown in FIG- URE (b) is selected, the combination of these two particular transistors giving the overall ,6 characteristic shown in FIGURE 10(0). The graphs of FIGURES 10(a)(c) all show 5 plotted as a function of frequency.

In FIGURE 11 of the drawings, there is shown another embodiment illustrating how a different currentgain characteristic can be obtained as a function of frequency for the basic NPN composite transistor of FIG- URE 1A. In this circuit, an input transistor 20 having the {3 characteristic 5 shown in the graph of FIGURE 11(a), is chosen. An output transistor 30 having the B characteristic 5 shown in the graph of FIGURE 11(b), is selected, the combination of two such transistors providing the overall current gain, 5 as shown in the graph of FIGURE 11(c). In comparing the currentgain characteristics of the circuits of FIGURES 10 and 11, it is seen that a high-pass filter characteristic is provided in the circuit of FIGURE 10 by choosing an input transistor having a lower cutoff frequency than the [3 of the output transistor, whereas in the circuit of FIGURE 11 a low-pass net characteristic is obtained by selecting an input transistor having a higher cutoff frequency than the B of the output transistor. It will be readily apparent to those skilled in the art that different bandpass characteristics are obtainable upon proper selection of the individual transistors. Furthermore, these concepts are equally applicable to provide desired bandpass characteristics for the composite PNP transistor of the circuit of FIGURE 1B.

In FIGURE 12 of the drawings, there is illustrated an embodiment of the present invention circuitry wherein transistors of the multiple emitter type are used to provide a NOR gate circuit. The embodiment of FIGURE 12 is based upon the circuit of FIGURE 1A, substituting multiple emitter transistors for both the input and output transistors of that circuit. A discussion of the theory and operation of multiple emitter transistors may be found in copending US. patent application, Serial No. 136,841, filed September 8, 1961, by James L. Buie, this patent application also being assigned to the present assignee.

Referring specifically to FIGURE 12, the input transistor is of the three emitter type and is designated by the reference numeral 270, the output transistor being of the two emitter type and designated by the reference numeral 280. The multiple emitter input transistor 270 is of the PNP type and includes a base electrode 271, emitter electrodes 272274 and a collector electrode 275. The multiple emitter output transistor 280 is of the NPN type and includes a base electrode 281, emitter electrodes 282 and 283, and a collector electrode 284. The base electrodes 271 and 281 of the transistors 270 and 280 are interconnected by an electrical lead 276. The collector electrode 275 of the transistor 27%) is interconnected with the emitter electrode 283 of the transistor 280 by an electrical lead 277, the electrical lead 277 being grounded, as shown. The emitter electrodes 272, 273 and 274 are connected to respective input terminals 285, 286 and 287. The collector electrode 284 of the output transistor 28%) is connected to an output terminal 288. The base electrode 281 and the emitter electrode 232 of the transistor 28% are interconnected by an electrical lead 278 to provide an anti-saturation feature, as will be further discussed hereinbelow. A common terminal 289 is connected to the grounded electrical lead 277.

A NOR gate is a multiple input logic circuit which produces an output whenever a triggering signal is impressed on any of its inputs, the polarity of the output signal being opposite to the polarity of the input signal, i.e., a NOR gate is an OR gate with phase inversion. The usual transistor logic to provide a NOR function utilizes either a plurality of transistors, the input electrode of each transistor forming one of the gate inputs, or a single transistor having its input electrode coupled to each input through a separate D.C. isolating means. In the circuit of FIGURE 12, on the other hand, all of the inputs are directly coupled to a single input transistor. Thus, the circuit of FIGURE 1'2 provides composite directly coupled transistor logic having an overall circuit 5 which is substantially insensitive to changes in temperature and radiation level. In the circuit of FIGURE 12 the interconnection of the base electrode 2% and the emitter electrode 282 by the electrical lead 278 provides a current-regulating feedback effect which prevents deep saturation of the transistor 280, thereby reducing its storage time and so increasing circuit speed. It will be readiiy apparent to those skilled in the art that the present invention concepts are equally applicable to other types of transistor logic, such as AND gate circuitry, for example.

Thus there has been described composite circuitry which is electrically equivalent to an electrical translating element and which is characterized by a current gain which is relatively insensitive to temperature changes and radiation levels, various embodiments and uses of the basic circuitry being shown. Although the invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example and that numerous changes in the details of construction and the combination and arrangement of parts may be resorted to without departing from the spirit and scope of the invention as hereinafter claimed. Any transistor type presently available, with the exception of point contact devices, may be used in any of the present invention embodiments.

ll What is claimed is: 1. A transistor circuit forming a composite electrical translating element havingan input electrode, an output "electrode and a common electrode, said circuit comprising:

(a) an input transistor having a base electrode, an

emitter electrode and a collector electrode, the emitterelectrode of said input transistor serving as the input electrode of said composite electrical translating element;

(b) an outputtransistor having a base electrode, an emitter electrode and a collector electrode, said output transistor being of the opposite conductivity type from said input transistor, the collector electrodes of said output transistor serving as the output electrode of said composite electrical translating element, the base electrode of said output transistor and the base electrode of said input transistor being interconnected only to each other; and,

(c) means interconnecting the emitter electrode of said output transistor with the collector electrode of said input transistor, said means serving as the common terminal of said composite electrical translating element.

2. A transistor circuit forming a composite electrical translating element having an input electrode, an output electrode and a common electrode, said circuit comprising:

(a) an input transistor having a base electrode, an

emitter electrode and a collector electrode, the emitter electrode of said input transistor serving as the input electrode of said composite electrical translating element;

(b) an output transistor having a base electrode, an emitter electrode and a collector electrode, said output transistor being of the opposite conductivity type from said input transistor, the collector electrode of said output transistor serving as the output electrode of said composite electrical translating element, the base electrode of said output transistor being directly connected to the base electrode of said input transistor; and,

(c) means directly interconnecting the emitter electrode of said output transistor with the collector electrode of said input transistor, said means serving as the common terminal of said composite electrical translating element.

3. A transistor circuit forming acomposite electrical translating element having an input electrode, an output electrode and a common electrode, said circuit compris- (a) an input transistor having a base electrode, an

emitter electrode and a collector electrode, said input transistor having a current gain within the range of from about five to about fifty, the emitter electrode of said input transistor serving as the input electrode of said composite electrical translating element;

(b) an output transistor having a base electrode, an

emitter electrode and a collector electrode, said output transistor being of the opposite conductivity type from said input transistor, the current gain of said output transistor being Within the range of from about ten to about five hundred and being at least twice the current gain of said input transistor, the collector electrode of said output transistor serving as the output electrode of said composite electrical translating element, the base electrode of said output transistor being directly connected to the base electrode of said input transistor; and,

(c) means directly interconnecting the emitter electrode of said output transistor withthe collector electrode of said input transistor, said means serving as the common terminal of said compositeelectrical translatingelement. f

-4. A transistor circuit comprising, in combination:

(a) a signal input terminal;

(b) a signal output terminal;

(0) a signal common terminal;

((1) a first transistor having a base electrode, an emitter electrode and a collector electrode, the emitter electrode of said first transistor being coupled to said signal input terminal;

(e) a second transistor having a base electrode, an

emitter electrode and a collector electrode, said second transistor being of opposite conductivity type from said first transistor, the base electrode of said second transistor being coupledto the base electrode of said first transistor, the emitter electrode of said second transistor being coupled to the collector electrode of said first transistor, the collector electrode of said second transistor being coupled to said signal output terminal;

(f) a third transistor having a base electrode, an emitter electrode and a collector electrode, said third transistor being of the same conductivity type as said first transistor, the emitter electrode of said'third transistor being coupled to the emitter electrode of said second transistor, the collector electrode of said third transistor being coupled to said signal common terminal; and,

(g) a fourth transistor having a base electrode, an emitter electrode and a collector electrode, said fourth transistor being of the opposite conductivity type from. said first transistor, the base electrode of said fourth transistorbeing coupled to the base electrode of said third transistor, the emitter electrode of said fourth transistor being coupled to said signal common terminal, the collector electrode of said fourth transistor being coupled to said signal output terminal.

5. A transistor circuit comprising, in combination:

(a) a signal-input terminal;

' (b) a signal output terminal;

(0) a signal common terminal;

(d) a first transistor having a base electrode, an emitter electrode and a collector electrode, the emitter electrode of said first transistor being coupled to said signal input terminal;

(e) a second transistor having a base electrode, an

emitter electrode and a collector electrode, said second transistor being of the opposite conductivity type from said first transistor, the base electrode of said second transistor being coupled to the base electrode of said first transistor, theemitter electrode of said second transistor being coupled to the collector electrode of said first transistor and to said signal common terminal;

(f) a third transistor having a'base electrode, an emitter electrode and a collector electrode, said third transistor being of the same conductivity type as said first transistor, the emitter electrode of said third transistor being coupled to the collector electrode of said second transistor and to a source of direct current operating potential, the collector electrode of said third transistor being coupled to said signal common terminahand,

(g) a fourth transistor having a base electrode, an emitter electrode and a collector electrode, said fourth transistor being of the opposite conductivity type from said first transistor, the base electrode of said fourth transistor being coupled to the base electrode of said third transistor, the emitter electrode of said fourth transistor being coupled to said signal common terminal, the collector electrode of said fourth transistor being coupled to said signal output terminal.

6. A transistor circuit comprising, in combination:

(a) a signal input terminal;

(b) a signal output terminal;

23 (c) a signal common terminal; (d) a first transistor having a base electrode, an emitter electrode and a collector electrode, the emitter electrode of said first transistor being coupled to said (d) a capacitance coupled between the base and emitter electrodes of said output transistor. 8. A transistor circuit forming a composite electrical 14 (c) means interconnecting the emitter electrode of said output transistor with the collector electrode of said input transistor, said means serving as the common terminal of said composite electrical translating signal input terminal; element, and, (e) a second transistor having a base electrode, an (d) a capacitance coupled between the base and emitemitter electrode and a collector electrode, said ter electrodes of said input transistor. second transistor being of the opposite conductivity 9. A transistor circuit forming a composite electrical type from said first transistor, the base electrode of translating element having an input electrode, an output said second transistor being coupled to the base elec- 1O electrode and a common electrode, and exhibiting a bandtrode of said first transistor, the emitter electrode of pass filter characteristic, said circuit comprising: said second transistor being coupled to the collector (a) an input transistor having a base electrode, an electrode of said first transistor and to said signal emitter electrode and a collector electrode, the emitcommon terminal; ter electrode of said input transistor serving as the (f) a third transistor having abase electrode, an emitter 15 input electrode of said composite electrical translating electrode and a collector electrode, said third tranelement; sistor being of the opposite conductivity type from (-b) an output transistor having a base electrode, an said first transistor, the emitter electrode of said emitter electrode and a collector electrode, said outthird transistor being coupled to the collector elecput transistor being of the opposite conductivity type trode of said second transistor; from said input transistor, the collector electrode of (g) a fourth transistor having a base electrode, an said output transistor serving as the output electrode emitter electrode and a collector electrode, said fourth of said composite electrical translating element, the transistor being of the same conductivity type as said base electrode of said output transistor being coupled first transistor, the base electrode of said fourth tranto the base electrode of said input transistor; sistor being coupled to the base electrode of said (c) means interconnecting the emitter electrode of said third transistor, the emitter electrode of said fourth output transistor with the collector electrode of said transistor being coupled to the collector electrode of input transistor, said means serving as the common said third transistor, the collector electrode of said terminal of said composite electrical translating elefourth transistor being coupled to said signal common ment; and, terminal and to said signal output terminal; and, (d) a first capacitor coupled between a base and emit- (h) a source of direct current operating potential ter electrodes of said output transistor; and,

coupled between said signal common terminal and the (e) a second capacitor coupled between the base and emitter electrode of said fourth transistor. emitter electrodes of said input transistor, the capac- 7. A transistor circuit forming a composite electrical itance of said second capacitor being a predetertranslating element having an input electrode, an output mined amount smaller than the capacitance of said electrode and a common electrode, and exhibiting a low first capacitor. pass filter characteristic, said circuit comprising: 10, A NOR gate cir uit comprising, in combination: (a) an input transistor having a base electrode, an (a) apredetermined plurality of signal input terminals;

emitter electrode and a collector electrode, the emit- (b) a signal output terminal; ter electrode of said input transistor serving as the a fi transistor h i a b electrode, id input electrode of said composite electrical translatd termin d plurality of emitter electrodes and a ing element; collector electrode, each of said emitter electrodes (b) an output transistor having a base electrode, an being coupled to a difierent one of said signal input emitter electrode and a collector electrode, said outterminals; and, put transistor being of the opposite conductivity type 5 (d) a second transistor having a base electrode, two from said input transistor, the collector electrode of emitter electrode and a collector electrode, said said input transistor serving as the output electrode of second transistor being of the opposite conductivity Said Composite electrical translating element, the type from said first transistor, the base electrode of as electrode of Said Output transistor being C pl d said second transistor being coupled to the base electo the base elect de Of S inp st trode of said first transistor, one of the emitter elec- (c) means interconnecting the emitter electrode of trodes of said second transistor being coupled to the said output transistor with the collector electrode of base electrode of said second transistor, the other Said input transistor, Said means Serving as the emitter electrode of said second transistor being mon terminal of said composite electrical translating l d to h collgctor electrode of id fi t tramelement; and, sistor, the collector electrode of said second transistor being coupled to the collector electrode of said first transistor, the collector electrode of said second transistor being coupled to said signal output terminal.

translating element having an input electrode, an output electrode and a common electrode, and exhibiting a highpass filter characteristic, said circuit comprising:

(a) an input transistor having a base electrode, an

emitter electrode and a collector electrode, the emitter electrode of said input transistor serving as the input electrode of said composite electrical translating element;

(b) an output transistor having a base electrode, an

emitter electrode and a collector electrode, said output transistor being of the opposite conductivity type from said input transistor, the collector electrode of said output transistor serving as the output electrode of said composite electrical translating element, the base electrode of said output transistor being coupled to the base electrode of said input transistor;

11. In a transistor circuit: a first transistor having a base electrode, an emitter electrode and a collector electrode; a second transistor having a base electrode, an emitter electrode and a collector electrode, said second transistor being of the opposite conductivity type from said first transistor; means interconnecting the base electrode of said second transistor to the base electrode of said first transistor; and, direct-current coupling means interconnecting the emitter electrode of said second transistor only with the collector electrode of said first transistor, input signals being applied between the emitter and collector electrodes of said first transistor, output signals appearing between the collector and emitter electrodes of said second transistor.

(References on following page) 15 1% References Cited by timeExaminerv 3,178,588 4/ 1965 Fuller 307-88.5 2 744 198 a??? PATENTS GEORGE N. WESTBY, Primary Examiner.

21S ec 2,860,260 11/ 1958 Sykes. 5 ARTHUR'GAUSS, DAVID .1. GALVIN, Exammers.

2,901,638 8/1959 Huang 307-88.5 B. P. DAVIS, Assistant Examiner. 

1. A TRANSISTOR CIRCUIT FORMING A COMPOSITE ELECTRICAL TRANSLATING ELEMENT HAVING AN INPUT ELECTRODE, AN OUTPUT ELECTRODE AND A COMMON ELECTRODE, SAID CIRCUIT COMPRISING: (A) AN INPUT TRANSISTOR HAVING A BASE ELECTRODE, AN EMITTER ELECTRODE AND A COLLECTOR ELECTRODE, THE EMITTER ELECTRODE OF SAID INPUT TRANSISTOR SERVING AS THE INPUT ELECTRODE OF SAID COMPOSITE ELECTRICAL TRANSLATING ELEMENT; (B) AN OUTPUT TRANSISTOR HAVING A BASE ELECTRODE, AN EMITTER ELECTRODE AND A COLLECTOR ELECTRODE, SAID OUTPUT TRANSISTOR BEING OF THE OPPOSITE CONDUCTIVITY TYPE FROM SAID INPUT TRANSISTOR, THE COLLECTOR ELECTRODES OF SAID OUTPUT TRANSISTOR SERVING AS THE OUTPUT ELECTRODE OF SAID COMPOSITE ELECTRICAL TRANSLATING ELEMENT, THE BASE ELECTRODE OF SAID OUTPUT TRANSISTOR AND THE BASE ELECTRODE OF SAID INPUT TRANSISTOR BEING INTERCONNECTED ONLY TO EACH OTHER; AND, (C) MEANS INTERCONNECTING THE EMITTER ELECTRODE OF SAID OUTPUT TRANSISTOR WITH THE COLLECTOR ELECTRODE OF SAID INPUT TRANSISTOR, SAID MEANS SERVING AS THE COMMON TERMINAL OF SAID COMPOSITE ELECTRICAL TRANSLATING ELEMENT. 